HPM6800 Series

The HPM6800 series is dedicated to providing single master digital instrument and HMI solutions. Its products have a clock frequency of up to 600MHz, a built-in RISC-V core, a computing power of up to 1710DMIPS, and support for enhanced image systems. This article mainly introduces the hardware design requirements for HPM6880 with single DDR2 or single DDR3L, and provides two types of DDR DEMO source files for reference. It is recommended that customers directly use the schematic and PCB provided by the DEMO for design.

Hpm_motor is a library file for core algorithms of motor control, which aims to continuously update and improve specific functional algorithms through modular management; For users, there is no need to worry about how the underlying implementation is implemented, which accelerates the development of user programs. Trajectory planning algorithm: When the motor starts and stops, there is a step change in speed. Sudden changes in motor speed may lead to current overload. So, acceleration and deceleration control algorithms are usually used to plan motor speed. The trajectory planning algorithm used in libhpm_motor. a is an S-shaped curve, whose core function is to control the change of acceleration by varying the magnitude of acceleration, ensuring that the acceleration does not suddenly change, making the acceleration and deceleration speed curves smooth, thereby achieving the goal of smooth operation of the motor

This plan mainly introduces how to use the built-in SEC_IMG-OFFSET function of bootrom for OTA upgrade. We use UART xmodem function for OTA upgrade and run encrypted firmware.

This solution is a customized Level 2 Boot upgrade solution that supports firmware upgrades in both Level 2 Boot and APP applications. Support upgrade package creation and support different verification algorithms, such as checksum/xor/crc32/sha1/sha256/sm3; Support ping/pang upgrade, second level Boot supports remap jump, user-app only requires one project and linker file; Level 2 Boot supports version verification and intelligent redirection.

This scheme triggers ADC sampling at a specific PWM moment, and at the same time triggers HDMA to operate SPI controller at another specific PWM point. It relies on HDMA chain mode to create a circular linked list, and HDMA automatically completes SPI read and write tasks, storing the read data in the designated memory without CPU involvement. At the same time, the HPM ADC controller also has its own DMA, which stores the sampled data in the designated memory after ADC sampling is completed, and the CPU does not need to participate. Users can directly use the ADC sampling results and SPI encoder information in the ADC sampling completion interrupt to perform subsequent closed-loop algorithms and ultimately adjust the PWM duty cycle for the next cycle.

The HPM Power solution summarizes the requirements of power management MCU, integrates them into a universal software architecture solution, and provides various API interfaces. The HPM Power Driver API is a driver API interface for power supplies based on the HPM Software Development Kit (HPM SDK) package. The Power API abstracts hardware components such as PWM pairs, PWM, and ADC channels into custom ID numbers, and upper layer applications only need to focus on the abstract ID numbers.

Onboard 16MB Flash, 16GB eMMC, 512MB DDR3L, supports gigabit Ethernet, audio output, LVDS/MIPI display interfaces, MIPI/DVP camera, HS USB OTG, and includes a board-level debugger and a standard 20-pin JTAG interface. It also supports Raspberry Pi, CAN, LED, buttons, and other functions for ease of development.

Package: BGA417